1. Field of the Invention
The present invention relates to a device for the jump-like addressing of specific lines of a serially operating digital memory.
2. Description of the Related Art
Serially operating memories comprise a memory matrix consisting of memory cells arranged in rows and columns in a matrix form and decoders or other control devices, for example control chains (see, for example, the German Patent Application P 195 12 791.9, which are also called pointers.
The memory matrix contains, in addition to the memory cells, bit lines and word lines running at right angles to the latter. Each memory cell is connected to a bit line and is driven by a word line.
If a word line is addressed by a word decoder or, for example, by a word control chain or pointer, that is to say if it is selected, then the memory cells on this word line deliver their information to the bit lines assigned to them. Subsequently, via a bit decoder or, for example, a bit control chain, one of the bit lines and hence the information of a specific memory cell is addressed, that is to say selected.
In sequentially operating memories, this process takes place continuously, so that all the memory cells are addressed consecutively. However, in order to obtain information from the memory which can be corrected as far as possible (redundant codes), the cells of one word line or bit line must not be read out directly one after the other. In the case of completely faulty bit lines or word lines, the information content of the memory cell could in this case no longer be corrected. However, failures of adjacent word lines and bit lines occur very frequently. It is therefore beneficial to arrange the bit decoders or word decoders or control chains in such a way that they never drive the directly adjacent lines when the selection lines are changed. Such a method is designated here as, in particular, sequential, jump-like addressing.
Using the normal binary decoders, this jump-like addressing can be achieved in several ways:
1) For example, the binary address fed to the decoders is not increased continuously but with regular jumps. PA0 2) The decoders are constructed in such a way that, if the binary address fed to a decoder is increased continuously, outputs from the decoder are jumped over at regular intervals. PA0 3) The binary address is divided into a jump address and a selection address. Because of the binary addresses, such a division of the address permits only group sizes which are an integer part of all the lines to be selected, otherwise not all the lines are selected or some addresses select no lines, so that so-called empty addresses are produced. If it is intended to achieve jumps which are an integer part of all the lines to be selected, then the binary address must be increased using these jumps. This condition is required for serially operated memories see the abovementioned German reference P 195 12 791.9).